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authorH. Peter Anvin <hpa@zytor.com>2016-10-14 06:24:03 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-10-14 06:52:09 (GMT)
commit411d345192ee0c14a57334c01b2638586b0bcad9 (patch)
treefdbfa3db6bd89bcf4a6be2f9f17c67f20a3bf563
parentc07de56eb72f7bfe313d3dddd1ccfce87a0de209 (diff)
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abc80.v: make it possible to simulate a green or yellow screen
Make it possible to make the display green or yellow (should really be amber). Switches changed: SW[4] - suppress red (used for green) SW[3] - suppress blue (used for green or amber) SW[2] - V.24 instead of printer for serial port Add a new file to list the current LED/key/switch assignments.
-rw-r--r--CHANGES7
-rw-r--r--LEDS-SWITCHES26
-rw-r--r--abc80.v315
3 files changed, 192 insertions, 156 deletions
diff --git a/CHANGES b/CHANGES
index 74738e6..85253b3 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,3 +1,10 @@
+Changes in release DE1-20:
+--------------------------
+* See LEDS-SWITCHES for current assignment of LEDs, keys and switches.
+
+* Allow emulating a green or amber screen.
+
+
Changes in release DE1-19:
--------------------------
* Support an Olimex MOD-ENC28J60 Ethernet module attached to GPIO1
diff --git a/LEDS-SWITCHES b/LEDS-SWITCHES
new file mode 100644
index 0000000..1244cf6
--- /dev/null
+++ b/LEDS-SWITCHES
@@ -0,0 +1,26 @@
+ LEDG0 - disk (SD) activity (for real!)
+ LEDG1 - disk selected
+ LEDG2 - Ethernet selected
+ LEDG3 - CAS: relay (OUT 58,32)
+ LEDG4 - CAS: data out (OUT 58,64)
+ LEDG5 - turbo 3 (25 MHz)
+ LEDG6 - turbo 2 (12, 25 MHz)
+ LEDG7 - turbo 1 (6, 12, 25 MHz)
+
+ LEDR9-0 just show the status of SW9-0
+
+ KEY0 - Reveal text
+ KEY1 - Video mode test
+ KEY2 - CPU reset
+ KEY3 - Turbo mode
+
+ SW0 - SD card inserted
+ SW1 - SD card write protect
+ SW2 - physical serial port is V.24 not printer
+ SW3 - suppress blue (use for green or amber screen)
+ SW4 - suppress red (use for green screen)
+ SW5 - monitor calibration test pattern
+ SW6 - suppress blink
+ SW7 - reverse video
+ SW8 - no turbo (3 MHz default)
+ SW9 - 40 column default
diff --git a/abc80.v b/abc80.v
index f45b940..f8a45df 100644
--- a/abc80.v
+++ b/abc80.v
@@ -1,6 +1,6 @@
// -----------------------------------------------------------------------
-//
-// Copyright 2003-2014 H. Peter Anvin - All Rights Reserved
+//
+// Copyright 2003-2015 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -20,21 +20,21 @@
//
module abc80 (
- input clock_50, // 50 MHz clock
+ input clock_50, // 50 MHz clock
input [1:0] clock_24, // 24 MHz clock (on two pins)
input [1:0] clock_27, // 27 MHz clock (on two pins)
input ext_clock, // External clock input
inout ps2_clk, // PS/2 keyboard clock
inout ps2_dat, // PS/2 keyboard data
-
+
output [9:0] ledr, // Red LEDs
output [7:0] ledg, // Green LEDs
output [6:0] s7_0, // 7-segment LEDs
output [6:0] s7_1, // 7-segment LEDs
output [6:0] s7_2, // 7-segment LEDs
output [6:0] s7_3, // 7-segment LEDs
-
+
input [3:0] key_n, // Pushbutton switches
input [9:0] sw, // Slide switches
@@ -55,7 +55,7 @@ module abc80 (
output [1:0] dram_dqm, // SDRAM DQM (per byte)
output [11:0] dram_a, // SDRAM address bus
inout [15:0] dram_dq, // SDRAM data bus
-
+
output sram_ce_n, // SRAM CE#
output sram_oe_n, // SRAM OE#
output sram_we_n, // SRAM WE#
@@ -67,15 +67,15 @@ module abc80 (
inout sd_cmd, // SD card DI/MOSI/CMD
inout sd_dat0, // SD card SO/MISO/DAT0
inout sd_dat3, // SD card CS#/CD/DAT3
-
+
output uart_txd, // RS232 port TxD
input uart_rxd, // RS232 port RxD
-
+
output [3:0] vga_r, // VGA red
output [3:0] vga_g, // VGA green
output [3:0] vga_b, // VGA blue
output vga_hs, // VGA horz sync
- output vga_vs, // VGA vert sync
+ output vga_vs, // VGA vert sync
output aud_xck, // Audio master clock
output aud_bclk, // Audio bitclock
@@ -87,7 +87,7 @@ module abc80 (
inout i2c_scl, // I2C SCK line
inout i2c_sda, // I2C SDA line
- inout [35:0] gpio_0, // GPIO headers
+ inout [35:0] gpio_0, // GPIO headers
inout [35:0] gpio_1 // GPIO headers
);
@@ -95,12 +95,12 @@ module abc80 (
// PLLs and clock distribution
// ------------------------------------------------------------------------
- wire cpu_clk; // 25 MHz
+ wire cpu_clk; // 25 MHz
wire video_clk; // 18.75 MHz = compatible screen pixel rate
- wire fast_clk; // 100 MHz
- wire audio_clk; // 16 MHz = I2S master clock
- wire pll1_locked;
- wire pll2_locked;
+ wire fast_clk; // 100 MHz
+ wire audio_clk; // 16 MHz = I2S master clock
+ wire pll1_locked;
+ wire pll2_locked;
pll1 pll1 (
.inclk0 ( clock_50 ), // 50 MHz input clock
@@ -115,15 +115,15 @@ module abc80 (
.c0 ( audio_clk ), // x2/3 = 16 MHz
.locked ( pll2_locked )
);
-
+
// ------------------------------------------------------------------------
// Reset - synchronization and pulse stretch
// ------------------------------------------------------------------------
`define RESET_WIDTH 6 // 2^6 = 64 cycles minimum width
reg [`RESET_WIDTH:0] rst_ctr = 0;
- wire rst_n = rst_ctr[`RESET_WIDTH];
- reg power_rst_n = 1'b0;
-
+ wire rst_n = rst_ctr[`RESET_WIDTH];
+ reg power_rst_n = 1'b0;
+
always @(posedge cpu_clk)
if (~key_n[2] | ~pll1_locked | ~pll2_locked) // KEY2 = CPU reset
rst_ctr <= 0;
@@ -132,32 +132,32 @@ module abc80 (
always @(posedge cpu_clk)
power_rst_n <= 1'b1;
-
+
// ------------------------------------------------------------------------
// Standard LEDs (here so that we can switch around the LEDs more easily
// for quick debugging.)
// ------------------------------------------------------------------------
- wire [7:0] std_led;
- reg [6:0] std_s7_1;
- reg [6:0] std_s7_0;
+ wire [7:0] std_led;
+ reg [6:0] std_s7_1;
+ reg [6:0] std_s7_0;
reg [9:0] prog_ledr;
- reg [7:0] prog_led;
- reg [7:0] prog_s7_1;
- reg [7:0] prog_s7_0;
- reg [1:0] prog_led_ctl;
+ reg [7:0] prog_led;
+ reg [7:0] prog_s7_1;
+ reg [7:0] prog_s7_0;
+ reg [1:0] prog_led_ctl;
+
+ wire [7:0] sd_errled;
- wire [7:0] sd_errled;
-
// Show the switch status
assign ledr = prog_led_ctl[1] ? prog_ledr : sw;
assign ledg = prog_led_ctl[0] ? prog_led : std_led;
assign s7_3 = ~prog_s7_1[6:0];
assign s7_2 = ~prog_s7_0[6:0];
- assign s7_1 = sd_errled[7] ? ~7'b1111001 : ~std_s7_1[6:0];
- assign s7_0 = sd_errled[7] ? ~sd_errled[6:0] : ~std_s7_0[6:0];
-
+ assign s7_1 = sd_errled[7] ? ~7'b1111001 : ~std_s7_1[6:0];
+ assign s7_0 = sd_errled[7] ? ~sd_errled[6:0] : ~std_s7_0[6:0];
+
// ------------------------------------------------------------------------
// Timers
// ------------------------------------------------------------------------
@@ -171,12 +171,12 @@ module abc80 (
// obtain a 16 us clock, which then is divided by 8 for 128 us and by
// 625*2 for the 50 Hz clock. Note the last stage is always divide by 2,
// so we get 50% duty cycle. I'm so anal-retentive.
-
- reg [8:0] clk_div0; // 16 us counter
- reg [2:0] clk_div1; // 128 us counter
- reg [9:0] clk_div2; // 10 ms counter
- reg clk_div3; // 20 ms counter
-
+
+ reg [8:0] clk_div0; // 16 us counter
+ reg [2:0] clk_div1; // 128 us counter
+ reg [9:0] clk_div2; // 10 ms counter
+ reg clk_div3; // 20 ms counter
+
wire ctr_128us; // 128 us counter out
wire ctr_20ms; // 20 ms counter out
@@ -186,11 +186,11 @@ module abc80 (
clk_div0 <= 9'd399;
else
clk_div0 <= clk_div0-1;
-
+
if ( clk_div0 == 0 )
begin
clk_div1 <= clk_div1 + 1; // No special wrapping needed
-
+
if ( clk_div2 == 0 )
clk_div2 <= 10'd624;
else
@@ -203,43 +203,43 @@ module abc80 (
assign ctr_128us = clk_div1[2];
assign ctr_20ms = clk_div3;
-
+
// ------------------------------------------------------------------------
// Common bus wires declaration
// ------------------------------------------------------------------------
- wire [15:0] cpu_a; // Output address from CPU (used for IORQ)
- wire [19:0] mmu_a; // Output address from MMU (within a device)
- reg [7:0] msel; // Decoded device selects for MREQ
- reg [7:0] cpu_di; // Input data to CPU
- wire [7:0] cpu_do; // Output data from CPU
- wire cpu_m1_n; // M1# from CPU
- wire cpu_iorq_n; // IORQ# from CPU
- wire cpu_mreq_n; // MREQ# from CPU
- wire cpu_rd_n; // RD# from CPU
- wire cpu_wr_n; // WR# from CPU
- wire cpu_rfsh_n; // RFSH# from CPU
- wire cpu_halt_n; // HALT# from CPU
- wire cpu_busak_n; // BUSAK# from CPU (not used)
- wire cpu_int_n; // INT# to CPU
- wire cpu_nmi_n; // NMI# to CPU
+ wire [15:0] cpu_a; // Output address from CPU (used for IORQ)
+ wire [19:0] mmu_a; // Output address from MMU (within a device)
+ reg [7:0] msel; // Decoded device selects for MREQ
+ reg [7:0] cpu_di; // Input data to CPU
+ wire [7:0] cpu_do; // Output data from CPU
+ wire cpu_m1_n; // M1# from CPU
+ wire cpu_iorq_n; // IORQ# from CPU
+ wire cpu_mreq_n; // MREQ# from CPU
+ wire cpu_rd_n; // RD# from CPU
+ wire cpu_wr_n; // WR# from CPU
+ wire cpu_rfsh_n; // RFSH# from CPU
+ wire cpu_halt_n; // HALT# from CPU
+ wire cpu_busak_n; // BUSAK# from CPU (not used)
+ wire cpu_int_n; // INT# to CPU
+ wire cpu_nmi_n; // NMI# to CPU
// RETI# is a non-Z80 signal indicating that a RETI has been
// executed. We provide it in the CPU core because it is not feasible
// for I/O devices to snoop the bus.
- wire cpu_reti_n; // RETI# from CPU
-
+ wire cpu_reti_n; // RETI# from CPU
+
// ABC-bus decoded strobes
- reg [7:0] abc_out_n;
- reg [7:0] abc_in_n;
-
+ reg [7:0] abc_out_n;
+ reg [7:0] abc_in_n;
+
// ------------------------------------------------------------------------
// Keyboard controller
// ------------------------------------------------------------------------
- wire [7:0] kb_data; // Keyboard symbol output
- wire [7:0] kb_stat; // Keyboard status word
+ wire [7:0] kb_data; // Keyboard symbol output
+ wire [7:0] kb_stat; // Keyboard status word
// Keyboard status word:
// 7..0 = Strobe CapsLock NumLock ScrollLock Super Alt Ctrl Shift
-
+
keyboard keyboard (
.clkin ( cpu_clk ),
.reset_n ( rst_n ),
@@ -258,27 +258,27 @@ module abc80 (
// -- necessary to multiplex with the SRAM.
// ------------------------------------------------------------------------
- reg [5:0] fgxaddr; // Byte address horizontally
- reg [8:0] fgyaddr; // Byte address vertically (bit 0 ignored)
- reg [7:0] fgdata;
- wire fgxrst;
+ reg [5:0] fgxaddr; // Byte address horizontally
+ reg [8:0] fgyaddr; // Byte address vertically (bit 0 ignored)
+ reg [7:0] fgdata;
+ wire fgxrst;
reg [1:0] fgxrst_q;
- wire fgyrst;
- reg [1:0] fgyrst_q;
- wire fgack;
+ wire fgyrst;
+ reg [1:0] fgyrst_q;
+ wire fgack;
reg [1:0] fgack_q;
- reg [7:0] fgctl;
- reg [4:0] fgpage; // Which 16K page in SRAM
+ reg [7:0] fgctl;
+ reg [4:0] fgpage; // Which 16K page in SRAM
always @(posedge cpu_clk)
fgack_q <= { fgack_q[0], fgack };
always @(posedge cpu_clk)
fgxrst_q <= { fgxrst_q[0], fgxrst };
-
+
always @(posedge cpu_clk)
fgyrst_q <= { fgyrst_q[0], fgyrst };
-
+
always @(posedge cpu_clk)
begin
if (fgxrst_q[0] & ~fgxrst_q[1])
@@ -294,22 +294,22 @@ module abc80 (
// fgyaddr[0] ignored due to double-scanning
wire [18:0] sram_fgaddr = { fgpage, fgyaddr[8:1], fgxaddr };
-
+
wire sram_fgreq = fgack_q[0] & ~fgack_q[1];
// ------------------------------------------------------------------------
// Video controller
// ------------------------------------------------------------------------
- wire [10:0] video_a;
- wire [7:0] video_d;
- wire [10:0] chargen_a;
- wire [7:0] chargen_d; // Only the low 6 bits are actually used
- wire [2:0] rgb;
- wire [7:0] vram_do;
- wire [7:0] cgen_do;
- reg video_width;
-
+ wire [10:0] video_a;
+ wire [7:0] video_d;
+ wire [10:0] chargen_a;
+ wire [7:0] chargen_d; // Only the low 6 bits are actually used
+ wire [2:0] rgb;
+ wire [7:0] vram_do;
+ wire [7:0] cgen_do;
+ reg video_width;
+
videoram video_ram (
.wren_a ( 0 ),
.address_a ( video_a ),
@@ -321,7 +321,7 @@ module abc80 (
.q_b ( vram_do ),
.clock_b ( fast_clk )
);
-
+
chargen char_gen (
.wren_a ( 0 ),
.address_a ( chargen_a ),
@@ -333,7 +333,7 @@ module abc80 (
.q_b ( cgen_do ),
.clock_b ( fast_clk )
);
-
+
display video (
.clk ( video_clk ),
.width ( video_width ),
@@ -356,9 +356,12 @@ module abc80 (
.fg_yrst ( fgyrst )
);
- assign vga_r = {4{rgb[2]}};
- assign vga_g = {4{rgb[1]}};
- assign vga_b = {4{rgb[0]}};
+ // SW[4] and SW[3] can be used to emulate a green or amber monitor
+ // for the normal ABC80 screen, while still allowing colors to be
+ // shown, just permuted.
+ assign vga_r = {4{rgb[2] ^ (sw[4] & rgb[1])}};
+ assign vga_g = {4{rgb[1]}};
+ assign vga_b = {4{rgb[0] ^ (sw[3] & rgb[1])}};
// ------------------------------------------------------------------------
// External SRAM
@@ -370,18 +373,18 @@ module abc80 (
// unit in the future.
// ------------------------------------------------------------------------
- wire [7:0] sram_do; // Data out from sram
+ wire [7:0] sram_do; // Data out from sram
wire sram_oe_w;
wire sram_we_w;
- reg sram_we_q1;
- reg sram_we_q2;
- reg sram_fgrd;
+ reg sram_we_q1;
+ reg sram_we_q2;
+ reg sram_fgrd;
// Are we actually accessed by the CPU?
wire sram_cpu = msel[0] & cpu_clk_en;
-
- assign sram_oe_w = (sram_cpu & ~cpu_rd_n) | sram_fgrd;
- assign sram_we_w = sram_cpu & ~cpu_wr_n;
+
+ assign sram_oe_w = (sram_cpu & ~cpu_rd_n) | sram_fgrd;
+ assign sram_we_w = sram_cpu & ~cpu_wr_n;
always @(negedge rst_n or posedge fast_clk)
if ( ~rst_n )
@@ -402,16 +405,16 @@ module abc80 (
wire [18:0] sram_addr = sram_cpu ? mmu_a[18:0] : sram_fgaddr;
// Driving output pins.
-
+
assign sram_a = sram_addr[18:1];
assign sram_be_n = sram_addr[0] ? ~2'b10 : ~2'b01;
-
+
assign sram_ce_n = ~(sram_cpu | sram_fgrd);
assign sram_oe_n = ~sram_oe_w;
assign sram_we_n = ~(sram_we_w & ~sram_we_q2);
assign sram_dq = sram_we_w ? { cpu_do, cpu_do } : 16'bz;
-
+
// SRAM Input side MUX
assign sram_do = sram_addr[0] ? sram_dq[15:8] : sram_dq[7:0];
@@ -423,7 +426,7 @@ module abc80 (
sram_fgrd <= 1'b0;
fgdata <= sram_do;
end
-
+
// ------------------------------------------------------------------------
// External flash ROM
// Note: the flash ROM is a 70 ns part. With MMU delays, we have about
@@ -436,17 +439,17 @@ module abc80 (
// the low 1 MB due to MMU limitations.
// ------------------------------------------------------------------------
- reg [7:0] flsh_do; // Data out from flash
- wire flsh_oe_w = msel[1] & ~cpu_rd_n;
- reg [1:0] flsh_wait_ctr = 2'b00;
- wire flsh_wait_n = ~(flsh_oe_w & ~flsh_wait_ctr[1]);
-
+ reg [7:0] flsh_do; // Data out from flash
+ wire flsh_oe_w = msel[1] & ~cpu_rd_n;
+ reg [1:0] flsh_wait_ctr = 2'b00;
+ wire flsh_wait_n = ~(flsh_oe_w & ~flsh_wait_ctr[1]);
+
assign fl_rst_n = rst_n;
assign fl_oe_n = 1'b0; // Flash always output
assign fl_we_n = 1'b1; // Treat the flash as readonly
assign fl_ce_n = ~flsh_oe_w;
assign fl_a = { 2'b00, mmu_a };
-
+
always @(negedge rst_n or posedge cpu_clk)
if (~rst_n)
flsh_wait_ctr <= 2'b00;
@@ -460,7 +463,7 @@ module abc80 (
always @(posedge fast_clk)
flsh_do <= fl_dq;
-
+
// ------------------------------------------------------------------------
// BASIC patching ROM for 80-column mode
// ------------------------------------------------------------------------
@@ -475,25 +478,25 @@ module abc80 (
);
// The patching itself is now done in the CPU data input
-
+
// ------------------------------------------------------------------------
// MMU and memory address decoding
// ------------------------------------------------------------------------
wire [15:0] mmu_q; // The actual bits coming out of the MMU
- wire [2:0] mmu_devsel; // Undecoded device selects
- wire mmu_patch; // Patch BASIC?
-
- reg [9:0] mmu_mod_addr; // Modify address holding register
- reg [7:0] mmu_mod_data; // Modify data holding register (low byte)
+ wire [2:0] mmu_devsel; // Undecoded device selects
+ wire mmu_patch; // Patch BASIC?
+
+ reg [9:0] mmu_mod_addr; // Modify address holding register
+ reg [7:0] mmu_mod_data; // Modify data holding register (low byte)
- wire mmu_wr_e; // MMU write enable
- wire [15:0] mmu_rd_data; // Read data output from MMU
+ wire mmu_wr_e; // MMU write enable
+ wire [15:0] mmu_rd_data; // Read data output from MMU
- reg [3:0] mmu_map_sel; // WWRR
- wire [1:0] mmu_map;
+ reg [3:0] mmu_map_sel; // WWRR
+ wire [1:0] mmu_map;
- assign mmu_map =
+ assign mmu_map =
~cpu_wr_n ? mmu_map_sel[3:2] :
mmu_map_sel[1:0];
@@ -509,10 +512,10 @@ module abc80 (
.clock ( fast_clk )
);
- assign mmu_patch = mmu_q[15];
- assign mmu_devsel = mmu_q[14:12];
- assign mmu_a[19:8] = mmu_q[11:0];
- assign mmu_a[7:0] = cpu_a[7:0];
+ assign mmu_patch = mmu_q[15];
+ assign mmu_devsel = mmu_q[14:12];
+ assign mmu_a[19:8] = mmu_q[11:0];
+ assign mmu_a[7:0] = cpu_a[7:0];
always @(posedge fast_clk)
begin
@@ -559,13 +562,13 @@ module abc80 (
wire pr_cts;
wire pr_rxd;
wire pr_rts;
-
+
always @(posedge cpu_clk)
begin
pioa_ai[6:0] <= kb_data[6:0]; // 7 bit ASCII
pioa_ai[7] <= kb_stat[7]; // Strobe
end
-
+
T80PIO pioa (
.CLK_n ( cpu_clk ),
.RESET_n ( rst_n ),
@@ -584,7 +587,7 @@ module abc80 (
.ASTB_n ( ctr_128us ),
.BSTB_n ( /* == piob.astb_n */ 1 )
);
-
+
T80PIO piob (
.CLK_n ( cpu_clk ),
.RESET_n ( rst_n ),
@@ -610,17 +613,17 @@ module abc80 (
assign v24_cts = piob_ao[4];
// Pin assignments for V.24
- assign v24_dtr = ~sw[3];
+ assign v24_dtr = ~sw[2];
assign v24_rts = 1'b0;
- assign v24_rxd = sw[3] ? uart_rxd : 1'b1;
+ assign v24_rxd = sw[2] ? uart_rxd : 1'b1;
// Outbound UART port
- assign uart_txd = sw[3] ? v24_txd : pr_txd;
+ assign uart_txd = sw[2] ? v24_txd : pr_txd;
// Inbound printer signals
assign pr_cts = 1'b0;
- assign pr_rxd = sw[3] ? 1'b1 : uart_rxd;
-
+ assign pr_rxd = sw[2] ? 1'b1 : uart_rxd;
+
// Cassette outputs
assign cas_relay = piob_ao[5];
assign cas_output = piob_ao[6];
@@ -630,16 +633,16 @@ module abc80 (
//assign p1_a29 = cas_relay;
//assign p1_a28 = cas_output;
//assign cas_input = p1_a38;
-
+
assign std_led[3] = cas_relay;
assign std_led[4] = cas_output;
-
+
// ------------------------------------------------------------------------
// ABC-bus
// ------------------------------------------------------------------------
-
+
wire abc_sel;
-
+
always @(*)
begin
if ( abc_sel & ~cpu_wr_n )
@@ -655,7 +658,7 @@ module abc80 (
endcase // case( cpu_a[2:0] )
else
abc_out_n = ~8'h00;
-
+
if ( abc_sel & ~cpu_rd_n )
case ( cpu_a[2:0] )
3'b000: abc_in_n = ~8'h01;
@@ -712,7 +715,7 @@ module abc80 (
// Printer controller
wire [7:0] abc_pr_di;
wire pr_select;
-
+
printer printer (
.reset_n ( rst_n ),
.clk ( cpu_clk ),
@@ -751,7 +754,7 @@ module abc80 (
.eth_sck ( eth_sck ),
.eth_miso ( eth_miso ),
- .abc_do ( cpu_do ),
+ .abc_do ( cpu_do ),
.abc_di ( abc_eth_di ),
.abc_out_n ( abc_out_n[0] ),
.abc_cs_n ( abc_out_n[1] ),
@@ -765,7 +768,7 @@ module abc80 (
.select ( eth_select )
);
-
+
// The ENC28J60 module is attached to GPIO1 signals 26-33, corresponding
// to pins 29-38 (including power). This is dictated by VCC33 and GND
// on pins 29-30 corresponding to the MOD-ENC28J60 pins 1-2.
@@ -790,7 +793,7 @@ module abc80 (
assign std_led[0] = sd_active;
assign std_led[1] = sd_select;
assign std_led[2] = eth_select;
-
+
// Video width control INP 4 = 80, INP 3 = 40.
// Also allow KEY1 to flip it.
wire key1_debounced;
@@ -837,16 +840,16 @@ module abc80 (
reg [7:0] sound_sc0;
reg [7:0] sound_sc;
reg [3:0] i2c_ctr;
-
+
always @(posedge audio_clk)
begin
sound_sc0 <= sound; // Synchronize to audio_clk
sound_sc <= sound_sc0;
end
-
+
sound_i2s sound_i2s (
.i2s_clk (audio_clk),
-
+
.mixer_ctl ({sound_sc[5], sound_sc[3], sound_sc[4]}),
.vco_sel (sound_sc[2]),
.vco_pitch (sound_sc[1]),
@@ -882,7 +885,7 @@ module abc80 (
i2c_ctr <= 4'h0;
else
i2c_ctr <= i2c_ctr + 1;
-
+
sound_i2c sound_i2c (
.rst_n ( rst_n ),
.clk ( audio_clk ),
@@ -891,7 +894,7 @@ module abc80 (
.i2c_scl ( i2c_scl ),
.i2c_sda ( i2c_sda )
);
-
+
// ------------------------------------------------------------------------
// Internal non-ABC I/O registers (MMU, turbo, LED)
@@ -922,7 +925,7 @@ module abc80 (
prog_ledr <= 0;
prog_s7_0 <= 0;
prog_s7_1 <= 0;
-
+
intio_do <= ~8'b0;
fgctl <= 8'h00;
@@ -932,7 +935,7 @@ module abc80 (
begin
intio_do <= ~8'b0;
turbo_set <= 0;
-
+
if ( intio_sel & ~cpu_wr_n )
begin
casex ( cpu_a[5:0] )
@@ -1007,7 +1010,7 @@ module abc80 (
end // if ( intio_sel & ~cpu_rd_n )
end
end
-
+
// Turbo control: KEY3 = toggle turbo
wire key3_debounced;
wire key3_strobe;
@@ -1032,21 +1035,21 @@ module abc80 (
cpu_turbo <= cpu_do[1:0];
else if ( key3_strobe & key3_debounced )
cpu_turbo <= cpu_turbo - 1;
-
+
// ------------------------------------------------------------------------
// I/O address decoding
// ------------------------------------------------------------------------
wire [7:0] io_do;
-
+
// In original ABC80, A4 selected between the PIO and the bus controller
// (which included the sound generator.) We use A7 for our own devices.
// The PIO wants to see IORQ# and M1# directly.
-
+
assign pio_sel = ~cpu_a[7] & cpu_a[4];
assign abc_sel = ~cpu_iorq_n & cpu_m1_n & ~cpu_a[7] & ~cpu_a[4];
assign intio_sel = ~cpu_iorq_n & cpu_m1_n & cpu_a[7]; // Internal ports
-
+
// All I/O devices emit all ones when not selected, so we just AND together
// the outputs.
assign io_do = pioa_do & piob_do & intio_do & abc_do;
@@ -1080,7 +1083,7 @@ module abc80 (
// If cpu_turbo is 0, we want to execute at 3 MHz instead of 25
// ... which means enabling the clock 3 times every 25 cycles
//
- // 0 1
+ // 0 1
// cycle 0123456789ABCDEF012345678
// 3 MHz -------X-------X-------X-
// 6 MHz ---X---X---X---X---X---X-
@@ -1115,10 +1118,10 @@ module abc80 (
// T80 seems to not handle WAIT# quite right so do this via
// the clock enable instead...
assign cpu_clk_en = &(cpu_slow_ctr[2:0] | cpu_slow_mask)
- & flsh_wait_n & abc_wait_n;
+ & flsh_wait_n & abc_wait_n;
assign std_led[7:5] = cpu_slow_mask;
-
+
always @(*)
case ( cpu_turbo )
2'b00:
@@ -1164,5 +1167,5 @@ module abc80 (
.di ( cpu_di ),
.do ( cpu_do )
);
-
+
endmodule // abc80