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authorH. Peter Anvin <hpa@zytor.com>2016-11-17 23:30:30 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-17 23:32:58 (GMT)
commit25a68b7503ac63c384b2013ffa926539b9fad285 (patch)
tree4064d5cae9d15766a158eace381938a137eec93e
parent2abd7ac27970a28b33e9fc887fc4ee6adb553166 (diff)
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abc80.v: advance npled address on read/write, cleanups
When we access the npled config memory via port 157, advance the address pointer. This reduces the number of operations, and allows INIR/OTIR access to this memory. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--abc80.v57
1 files changed, 39 insertions, 18 deletions
diff --git a/abc80.v b/abc80.v
index 702c1ee..dfbb257 100644
--- a/abc80.v
+++ b/abc80.v
@@ -507,7 +507,7 @@ module abc80 (
reg [17:0] sram_addr_q;
reg [1:0] sram_be_q;
reg [15:0] sram_d_q; // Output data (from write)
- reg sram_d_en; // Data out enable
+ reg sram_d_en; // Data out enable
reg [15:0] sram_q; // Latched input data (in I/O pad)
reg sram_mux_ctl; // addr[0] with a delay
@@ -524,8 +524,8 @@ module abc80 (
// This is a *bit* address
wire [21:0] npled_addr;
- reg npled_do;
- reg [3:0] npled_addr_q; // Bit inside SRAM word, one cpu_clk delayed
+ reg npled_do;
+ reg [3:0] npled_addr_q; // Bit inside SRAM word, one cpu_clk delayed
always @(posedge cpu_clk)
npled_addr_q <= npled_addr[3:0];
@@ -1209,7 +1209,7 @@ module abc80 (
reg [35:0] gpio_ctl; // GPIO control word from CPU
reg [35:0] gpio_dat; // GPIO data word from CPU
wire [35:0] gpio_npled; // Mapping from npled channels to GPIOs
-
+
reg [35:0] gpio_din; // Data in register on pad
reg [35:0] gpio_ena; // Output enable register on pad
@@ -1259,7 +1259,7 @@ module abc80 (
always @(posedge fast_clk)
gpio_ena <= gpio_ctl | {36{np_enable}};
-
+
genvar pin;
generate
for (pin = 0; pin < 36; pin = pin + 1)
@@ -1272,9 +1272,10 @@ module abc80 (
// Internal non-ABC I/O registers (MMU, turbo, LED)
// ------------------------------------------------------------------------
- wire intio_sel; // Selected for access via I/O ports
- reg [7:0] intio_do; // Data out from MMU I/O ports
- reg iorq_q;
+ wire io_sel; // An actual I/O request, not INTAK
+ wire intio_sel; // Selected for access via I/O ports
+ reg [7:0] intio_do; // Data out from MMU I/O ports
+ reg io_sel_q;
reg turbo_set;
reg nmi_dis;
@@ -1283,6 +1284,8 @@ module abc80 (
reg [7:0] revrom_addr;
wire [7:0] revrom_q;
+ reg np_adv_addr; // Should np_cpu_addr be advanced?
+
revrom revrom (
.address ( revrom_addr ),
.clock ( fast_clk ),
@@ -1315,7 +1318,8 @@ module abc80 (
np_enable <= 1'b0;
np_cpu_addr <= 7'b0;
-
+ np_adv_addr <= 1'b0;
+
fgctl <= 8'h00;
fgpage <= 5'h05; // After BASIC80 in RAM
@@ -1324,13 +1328,21 @@ module abc80 (
revrom_addr <= 8'h00;
- iorq_q <= 1'b0;
+ io_sel_q <= 1'b0;
end
else
begin
- iorq_q <= ~cpu_iorq_n;
+ io_sel_q <= io_sel;
- if ( ~cpu_wr_n & ~cpu_iorq_n & cpu_m1_n & ~iorq_q &
+ // Advance np_cpu_addr after the IORQ# cycle is completed
+ if (~io_sel)
+ begin
+ np_adv_addr <= 1'b0;
+ np_cpu_addr <= np_cpu_addr + np_adv_addr;
+ end
+
+ // The MMU map responds to I/O ports abc_out[7] and 132-135.
+ if ( ~cpu_wr_n & io_sel & ~io_sel_q &
((cpu_a[7:2] == 6'b100001) |
(cpu_a[7] == 1'b0 & cpu_a[4:0] == 4'b0111)) )
begin
@@ -1343,7 +1355,7 @@ module abc80 (
intio_do <= ~8'h00;
turbo_set <= 1'b0;
end
- else if ( intio_sel & ~iorq_q & ~cpu_wr_n )
+ else if ( intio_sel & ~io_sel_q & ~cpu_wr_n )
begin
casez ( cpu_a[6:0] )
7'b0000000:
@@ -1379,7 +1391,12 @@ module abc80 (
np_enable <= cpu_do[7];
np_cpu_addr <= cpu_do[6:0];
end
- // 7'b0011101: np data write, decoded elsewhere
+ 7/b0011101:
+ begin
+ // np data write, the actual write happens
+ // elsewhere, but advance the address pointer
+ np_adv_addr <= 1'b1;
+ end
7'b0011110:
fgctl <= cpu_do[7:0];
7'b0011111:
@@ -1414,7 +1431,7 @@ module abc80 (
end
endcase // casez cpu_a[6:0] )
end // if ( intio_sel & ~cpu_wr_n )
- else if ( intio_sel & ~iorq_q & ~cpu_rd_n )
+ else if ( intio_sel & ~io_sel_q & ~cpu_rd_n )
begin
casez ( cpu_a[6:0] )
7'b0000000:
@@ -1455,7 +1472,10 @@ module abc80 (
7'b0011100:
intio_do <= { np_enable, np_cpu_addr[6:0] };
7'b0011101:
- intio_do <= np_cpu_di;
+ begin
+ intio_do <= np_cpu_di;
+ np_adv_addr <= 1'b1;
+ end
7'b0011110:
intio_do <= fgctl;
7'b0011111:
@@ -1533,8 +1553,9 @@ module abc80 (
// The PIO wants to see IORQ# and M1# directly.
assign pio_sel = ~cpu_a[7] & cpu_a[4];
- assign abc_sel = ~cpu_iorq_n & cpu_m1_n & ~cpu_a[7] & ~cpu_a[4];
- assign intio_sel = ~cpu_iorq_n & cpu_m1_n & cpu_a[7]; // Internal ports
+ assign io_sel = io_sel; // Actual I/O access (not INTAK)
+ assign abc_sel = io_sel & ~cpu_a[7] & ~cpu_a[4];
+ assign intio_sel = io_sel & cpu_a[7]; // Internal ports
// All I/O devices emit all ones when not selected, so we just AND together
// the outputs.