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authorH. Peter Anvin <hpa@zytor.com>2007-06-10 07:13:19 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2007-06-10 07:13:19 (GMT)
commit8643b4f97e287c8e133c6dc68f9601f53a3f6d02 (patch)
tree412a83657c0b1f45928d76b515a120f5b2103712
parent3bf05ad6c6cc4b95097bc1b7104914090f3c5f77 (diff)
downloadabc80-tv80.zip
abc80-tv80.tar.gz
abc80-tv80.tar.bz2
abc80-tv80.tar.xz
Document (eventual) switch to TV80tv80
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+Changes in release ??:
+----------------------
+* Switch from the T80 CPU (VHDL) to the TV80 CPU (Verilog).
+
Changes in release 18:
----------------------
* Cleanups to it synthesizes correctly under Quartus II 5.1 SP2.